This invention relates generally to three dimensional silicon integrated structures, and more specifically to the design and layout of through-silicon via (TSV) structures.
In recent years the development of three dimensional IC and silicon packaging (Si3D) has been proposed with through-silicon via (TSV) technology to enable the joining of multiple silicon chips and or wafers together that are mounted on a 2nd-level package.
In semiconductor technologies, a through-silicon via, also known as a through-substrate via, is a conductive feature formed in a semiconductor substrate (wafer or die). The TSV feature vertically passes through the semiconductor substrate, providing a stacked wafer/die packaging method and allowing electrical connection between circuits in separate wafers or chips.
There are a number of ways to create a TSV. Typically, a hole is etched into, and sometimes through, the semiconductor substrate, and the hole may then be lined with various isolating layers and/or various metal layers. The hole is then filled with the conductive material, typically copper (Cu), which becomes the major part of a TSV. Some TSV's are in electrical contact with the semiconductor substrate, while others are electrically isolated. Any material within the etched hole may be considered part of the TSV, so the complete TSV may include the Cu, plus a liner, and perhaps insulating layers. Initially, the hole may not extend through the complete depth of the wafer. One side of the wafer is then subject to a thinning process (e.g. mechanical grinding, chemical-mechanical-polishing (CMP), or chemical or plasma etching) until the conductive metal of the TSV extends all the way through the semiconductor substrate. This side of the semiconductor substrate may be referred to as the grind side. The opposite side, where devices and the interconnect structure are located, may be referred to as the device side.